1. Field of the Invention
The present invention is related to a flat panel display and a chip bonding pad. More particularly, the present invention is related to a flat panel display in which signal transmission impedances are matched and a chip bonding pad characterized by low impedance of signal transmission.
2. Description of Related Art
With an advancement of information industries, volume requirements for various displays result in miniaturization of the displays in the market. For instance, conventional cathode ray tube (CRT) displays have been replaced by flat panel displays including liquid crystal displays (LCDs), organic light emitting displays (OLEDs), and so on.
FIG. 1A is a schematic view of a conventional flat panel display. Referring to FIG. 1A, a flat panel display 100 includes a display panel 110, a plurality of flexible printed circuit (FPC) boards 120, a plurality of driving chips 130, and a control circuit board 140. The display panel 110 includes a display region A and a peripheral circuit region P. The driving chips 130 are disposed within the peripheral circuit region P. Besides, the driving chips 130 are electrically connected to the control circuit board 140 through the corresponding FPC boards 120.
Due to the increased dimension and resolution of the display panel 110, the number of the required driving chips 130 is increased accordingly. In order to enable all of the driving chips 130 to receive ground signals, power source signals, or other signals at a substantially equivalent level, an increase in the number of the FPC boards 120 is usually necessitated. Meanwhile, the length of the control circuit board 140 needs to be extended, such that all of the FPC boards 120 can be connected to the control circuit board 140. As such, material costs of the flat panel display 100 are raised because of the increased number of the FPC boards 120 and the increased area occupied by the control circuit board 140.
FIG. 1B is a partial top view illustrating a location where the driving chips are disposed on the display panel depicted in FIG. 1A. FIG. 1C is a cross-sectional view taken along a sectional line I-I′ of FIG. 1B. Referring to FIGS. 1A and 1B, the display panel 100 also includes a plurality of chip bonding pads 150 and 151 for connecting the driving chips 130. When the driving chips 130 are disposed on the display panel 110, the chip bonding pad 150 is then covered by the driving chips 130.
Next, as shown in FIGS. 1B and 1C, the chip bonding pad 150 includes a first conductive layer 152, a first dielectric layer 154, a second conductive layer 156, a second dielectric layer 158, and a third conductive layer 160 that are sequentially stacked. The first dielectric layer 154 has a plurality of first through holes 154A. The second dielectric layer 158 has a plurality of second through holes 158A and a plurality of third through holes 158B. The second through holes 158A correspond to the first through holes 154A for exposing a portion of the first conductive layer 152, while the third through holes 158B expose a portion of the second conductive layer 156. Besides, the third conductive layer 160 covers the second dielectric layer 158, the portion of the first conductive layer 152 exposed by the first through holes 154A, and the portion of the second conductive layer 156 exposed by the third through holes 158B.
The first through holes 154A and the third through holes 158B are juxtaposed in pairs. Thereby, signal transmission paths between the conductive layers in the chip bonding pad 150 merely have a single direction or path. For instance, when a signal is transmitted from the first conductive layer 152 to the second conductive layer 156, the signal is transmitted along a direction D. The third conductive layer 160 is often made of a transparent conductive material including an indium tin oxide. Hence, the third conductive layer 160 has a relatively great transmission impedance.